JTAG
1
Table 41. JTAG AC Timing Specifications (Independent of CLKIN) (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
JTAG external clock to output high impedance:
Boundary-scan data
TDO
ns
tJTKLDZ
tJTKLOZ
2
2
19
9
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see Figure 18).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going
to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK
.
5. Non-JTAG signal output timing with respect to tTCLK
.
6. Guaranteed by design and characterization.
Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 27. AC Test Load for the JTAG Interface
Figure 28 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTKHKL
tJTGR
tJTG
VM = Midpoint Voltage (OV /2)
tJTGF
DD
Figure 28. JTAG Clock Input Timing Diagram
Figure 29 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OV /2)
DD
Figure 29. TRST Timing Diagram
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
43
FREESCALE [ Freescale ]
