ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
76.2mm
76.2mm
Figure 18. 2s2p JDEC Thermal Test Board
(Red - Top Layer, Yellow - Two Buried Layers)
Figure 17. 1s JEDEC Thermal Test Board Layout
Transparent Top View
13 12 11 10
9
8
7
6
5
4
3
2
1
16
17
24
SO
FSI
23
GND
GND
14
GND
HS3
18
22
HS2
15
VPWR
MC10XS3412 Pin Connections
24-PIN PQFN (12 x 12)
0.9 mm Pitch
12.0mm 12.0mm Body
19
20
21
HS0
HS1
NC
Figure 19. Thermal Test Board
10XS3412
Analog Integrated Circuit Device Data
Freescale Semiconductor
47