ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
10XS3412
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 10XS3412
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
24-PIN
PQFN
Package and Thermal Considerations
This 10XS3412 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn
.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies
to RθJ21 and RθJ22, respectively.
98ARL10596D
24-PIN PQFN (12 x 12)
Note For package dimensions, refer to
98ARL10596D.
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 25. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
(1)(2)
RθJAmn
RθJBmn
RθJAmn
RθJCmn
26.04
13.21
46.42
0.67
18.18
6.40
35.49
23.94
53.82
0.00
(2)(3)
(1)(4)
(5)
0.2mm
37.03
0.95
Notes:
0.2mm
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
0.5mm dia.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
Figure 16. Detail of Copper Traces Under Device with
Thermal Vias
10XS3412
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
FREESCALE [ Freescale ]
