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10XS3412_12 参数 Datasheet PDF下载

10XS3412_12图片预览
型号: 10XS3412_12
PDF下载: 下载PDF文件 查看货源
内容描述: 四通道高边开关(双10毫欧,双12毫欧) [Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)]
分类和应用: 开关
文件页数/大小: 51 页 / 1411 K
品牌: FREESCALE [ Freescale ]
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FUNCTIONAL DEVICE OPERATION  
LOGIC COMMANDS AND REGISTERS  
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is  
replaced by OCHI2 during tOC1, as shown Figure 14.  
Xenon bit set to logic [0]:  
I
OCH1  
I
OCH1  
I
OCH2  
I
OCH2  
I
I
OC1  
OC2  
I
OC1  
OC2  
OC3  
OC4  
OCLO4  
OCLO3  
OCLO2  
OCLO1  
I
I
I
I
I
I
OCLO4  
OCLO3  
OCLO2  
OCLO1  
I
I
I
I
I
Time  
t
t
t
t
OC7  
t
OC3  
OC1  
t
t
OC5  
OC6  
OC4  
Time  
t
t
t
t
OC7  
t
OC3  
OC2  
OC1  
t
OC5  
OC6  
OC4  
t
OC2  
Xenon bit set to logic [1]:  
Figure 14. Over-current profile with OCHI bit set to ‘1’  
I
The wire harness is protected by one of four possible  
current levels in steady state, as defined in Table 18.  
OCH1  
OCH2  
I
I
I
I
I
OC1  
OC2  
OC3  
OC4  
Table 18. Output Steady State Selection  
OCLO1 (D2) OCLO0 (D1)  
Steady State Current  
I
I
I
I
OCLO4  
OCLO3  
OCLO2  
OCLO1  
0
0
1
1
0
1
0
1
OCLO2 (default)  
OCLO3  
OCLO4  
Time  
t
t
t
t
OC7  
t
OC3  
OC1  
t
t
OC5  
OC6  
OC4  
OCLO1  
OC2  
Bit D0 (OC_mode_sel) allows to select the over-current  
mode, as described Table 19.  
Figure 13. Over-current profile depending on Xenon bit  
D[7:6] bits allow to MCU to programmable bulb cooling  
curve and D[5:4] bits inrush curve for selected output, as  
shown Table 16 and Table 17.  
Table 19. Over-current Mode Selection  
OC_mode_s (D0)  
Over-current Mode  
Table 16. Cooling Curve Selection  
0
1
only inrush current management (default)  
BC1_s (D7)  
BC0_s (D6)  
Profile Curves Speed  
inrush current and bulb cooling  
management  
0
0
1
1
0
1
0
1
medium (default)  
slow  
ADDRESS 00101—GLOBAL CONFIGURATION  
REGISTER (GCR)  
fast  
medium  
The GCR register allows the MCU to configure the device  
through the SPI.  
Table 17. Inrush Curve Selection  
Bit D8 allows the MCU to enable or disable the VDD failure  
detector. A logic [1] on VDD_FAIL_en bit allows transitioning  
to Fail-safe mode for VDD < VDD(FAIL).  
OC1_s (D5)  
OC0_s (D4)  
Profile Curves Speed  
slow (default)  
fast  
0
0
1
1
0
1
0
1
Bit D7 allows the MCU to enable or disable the PWM  
module. A logic [1] on PWM_en bit allows control of the  
outputs HS[0:3] with PWMR register (the direct input states  
are ignored).  
medium  
very slow  
Bit D6 (CLOCK_sel) allows to select the clock used as  
reference by PWM module, as described in the following  
Table 20.  
10XS3412  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
36  
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