FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 11. Serial Input Address and Configuration Bit Map
SI Data
SI
Register
D1 D1 D1 D1 D1
D15
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4
3
2
1
0
STATR_s WDI
N
X
X
0
0
0
0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
PWMR_s WDI
N
A
A
0
0
0
1
1
1
X
0
1
1
0
0
1
X
1
0
1
0
1
1
X
0
0
0
0
0
0
0
28W_s
ON_s
PWM6_s
0
PWM5_s
PWM4_s
SR1_s
PWM3_s
SR0_s
PWM2_s
PWM1_s
PWM0_s
1
1
1
0
0
0
CONFR0 WDI
A
A
A
A
A
A
0
0
0
0
DIR_dis_s
DELAY2_s DELAY1_s DELAY0_s
_s
N
CONFR1 WDI
Retry_
unlimited_s
Retry_dis_ OS_dis_s OLON_dis_ OLOFF_dis_ OLLED_en CSNS_ratio
_s
N
s
s
s
_s
_s
OCR_s WDI
N
Xenon_ BC1_s
s
BC0_s
OC1_s
OC0_s
OCHI_s
OCLO1_s
OCLO0_s OC_mode_
s
1
0
GCR
WDI
N
0
0
VDD_F PWM_en CLOCK_sel TEMP_en CSNS_en
AIL_en
CSNS1
CSNS0
X
1
0
OV_dis
CALR
WDI
N
0
0
0
0
1
0
1
0
1
1
0
0
0
1
0
Register
state
0
0
0
0
0
0
after
RST=0 or
V
DD(FAIL)
or
V
SUPPLY(
POR)
condition
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 12.
DEVICE REGISTER ADDRESSING
Table 12. Output Selection
The following section describes the possible register
A1 (D14)
A0 (D13)
HS Selection
addresses (D[14:10]) and their impact on device operation.
0
0
1
1
0
HS0 (default)
HS1
ADDRESS XX000—STATUS REGISTER
(STATR_S)
1
0
1
HS2
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
section entitled Serial Output Communication (Device Status
Return Data) on page 37.
HS3
A logic [1] on bit D8 (28W_s) selects the 28 W over-
current protection profile: the over-current thresholds are
divided by 2 and, the inrush and cooling responses are
dedicated to 28 W lamp.
Bit D7 sets the output state. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown Table 7.
ADDRESS A A 001—OUTPUT PWM CONTROL
1
0
REGISTER (PWMR_S)
The PWMR_s register allows the MCU to control the state
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
of the D14:D13 bits (Table 12).
ADDRESS A A 010—OUTPUT CONFIGURATION
REGISTER (CONFR0_S)
1
0
The CONFR0_s register allows the MCU to configure
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14:D13 bits (Table 12).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D5
10XS3412
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
FREESCALE [ Freescale ]
