FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
POSITIVE POWER SUPPLY (VPWR)
HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)
This pin connects to the positive power supply and is the
source of operational power for the device. The VPWR
contact is the backside surface mount tab of the package.
Protected 10 mΩ and 12 mΩ high side power outputs to
the load.
FAIL SAFE INPUT (FSI)
SERIAL OUTPUT (SO)
This pin incorporates an active internal pull-up current
source from internal supply (VREG). This enables the
watchdog timeout feature.
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
the state of the key inputs, etc. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK. SO reporting descriptions are provided in Table 23.
When the FSI pin is opened, the watchdog circuit is
enabled. After a Watchdog timeout occurs, the output states
depends on IN[0:3].
When the FSI pin is connected to GND, the watchdog
circuit is disabled. The output states depends on IN[0:3] in
case of VDD Failure condition, in case VDD failure detection is
activated (VDD_FAIL_en bit sets to logic [1]).
10XS3412
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FREESCALE [ Freescale ]
