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10XS3412_12 参数 Datasheet PDF下载

10XS3412_12图片预览
型号: 10XS3412_12
PDF下载: 下载PDF文件 查看货源
内容描述: 四通道高边开关(双10毫欧,双12毫欧) [Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)]
分类和应用: 开关
文件页数/大小: 51 页 / 1411 K
品牌: FREESCALE [ Freescale ]
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ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 5. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, -40 °C TA 125 °C, GND = 0 V, unless  
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless  
otherwise noted.  
Characteristic  
SPI INTERFACE CHARACTERISTICS(36)  
Maximum Frequency of SPI Operation  
Symbol  
Min  
Typ  
Max  
Unit  
fSPI  
tWRST  
tCS  
10  
8.0  
MHz  
μs  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(37)  
Required Low State Duration for RST  
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(38)  
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(38)  
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(38)  
Required High State Duration of SCLK (Required Setup Time)(38)  
Required Low State Duration of SCLK (Required Setup Time)(38)  
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(38)  
SI to Falling Edge of SCLK (Required Setup Time)(39)  
Falling Edge of SCLK to SI (Required Setup Time)(39)  
SO Rise Time  
1.0  
5.0  
500  
50  
50  
60  
37  
49  
tENBL  
tLEAD  
tWSCLKh  
tWSCLKl  
tLAG  
tSI(SU)  
tSI(HOLD)  
tRSO  
C = 80 pF  
L
13  
SO Fall Time  
tFSO  
ns  
C = 80 pF  
L
13  
SI, CS, SCLK, Incoming Signal Rise Time(39)  
tRSI  
tFSI  
tSO(EN)  
tSO(DIS)  
13  
13  
60  
60  
ns  
ns  
ns  
ns  
SI, CS, SCLK, Incoming Signal Fall Time(39)  
Time from Rising Edge of SCLK to SO Low-impedance(40)  
Time from Rising Edge of SCLK to SO High-impedance(41)  
Notes  
36. Parameters guaranteed by design.  
37. RST low duration measured with outputs enabled and going to OFF or disabled condition.  
38. Maximum setup time required for the 10XS3412 is the minimum guaranteed time needed from the microcontroller.  
39. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.  
40. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.  
41. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.  
10XS3412  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
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