F81867
9bit-mode Slave Address Mask Register ⎯ Index F5h
Bit
Name
R/W Reset Default
Description
This byte accompanying with SADDR will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
11. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
12. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
that bit. The remaining bit which is “1” is compared to the received
address.
7:0
SADEN
R/W LRESET#
00h
Ex.
SADDR
SADEN
0101_1100b
1111_1001b
0101_1xx0b
1111_11x1b
Given Address
Broadcast Address
FIFO Select Register ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
0: TX will start transmit immediately after writing THR.
1: TX will delay 1 bit time to transmit after writing THR.
0: TX will assert interrupt when THR is empty.
1: TX will assert interrupt when THR and shift register is empty.
The RX FIFO threshold select.
7
TX_DEL_1BIT
R/W LRESET#
R/W LRESET#
0
0
6
TX_INT_MODE
00: FIFO threshold is set by RXFTHR.
5-4
RXFTHR_MODE
R/W LRESET#
0
01: FIFO threshold will be 2X of RXFTHR.
10: FIFO threshold will be 4X of RXFTHR.
11: FIFO threshold will be 8X of RXFTHR.
IRQ_MODE1 and IRQ_MODE0 will select the UART3 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
01 : Sharing IRQ active high edge mode.
10 : Sharing IRQ active high Level mode.
3
IRQ_MODE1
R/W LRESET#
0
-
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
Reserved.
2
Reserved
-
-
Select the FIFO depth.
00: 16-byte FIFO.
1-0
FIFO_MODE
R/W LRESET#
00h 01: 32-byte FIFO.
10: 64-byte FIFO.
11: 128-byte FIFO.
197
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
