F81867
7.9 WDT Registers (CR07)
“-“ Reserved or Tri-State
Default Value
Register 0x[HEX]
30
Register Name
WDT Device Enable Register
MSB
LSB
-
-
-
-
-
-
0
0
0
0
-
-
0
0
0
0
0
0
60
61
F5
F6
FA
Base Address High Register
Base Address Low Register
WDT Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
-
WDT Timer Register
WDT PME Enable Register
1
WDT Device Base Address Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
0
Reserved
0: disable WDT base address.
1: enable WDT base address.
0
WDT_EN
R/W 5VSB
0
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W 5VSB 00h The MSB of WDT base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
R/W 5VSB 00h The LSB of WDT base address.
Description
Description
7-0
BASE_ADDR_LO
Watchdog Control Configuration Register 1 ⎯ Index F5h
Bit
Name
R/W Reset Default
Reserved
7
Reserved
R
-
0
0
If watchdog timeout event occurred, this bit will be set to 1. Write a 1 to this
bit will clear it to 0.
6
WDTMOUT_STS
R/W 5VSB
If this bit is set to 1, the counting of watchdog time is enabled.
5
4
3
WD_EN
WD_PULSE
WD_UNIT
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
2
WD_HACTIVE
R/W 5VSB
0
Select output pulse width of RSTOUT#
1-0
WD_PSWIDTH
R/W 5VSB
0
0: 1 ms
2: 125 ms
1: 25 ms
3: 5 sec
Watchdog Timer Configuration Register 2 ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
Time of watchdog timer (0~255)
7-0
WD_TIME
R/W 5VSB
0
175
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
