F81867
Watchdog PME Enable Configuration Register 2 ⎯ Index FAh
Bit
Name
R/W Reset Default
Description
0: No WDT PME occurred.
1: WDT PME occurred.
7
WDT_PME
R
5VSB
0
The WDT PME is occurred one unit before WDT timeout.
0: Disable Watchdog PME.
1: enable Watchdog PME.
6
5
WDT_PME_EN
Reserved
R/W 5VSB
0
0
Reserved
R
-
WDT Clock Source Select
0: Internal 1KHz clock.
1: 1KHZ clock driven by CLKIN.
Reserved
4
WDT_CLK_SEL
R/W 5VSB
1
3-1
0
Reserved
R
-
0
0
0: disable Watchdog time out output via WDTRST#.
1: enable Watchdog time out output via WDTRST#.
WDOUT_EN
R/W 5VSB
7.10 PME, ACPI and EUP Registers (LDN 0x0A)
“-“ Reserved or Tri-State
Register 0x[HEX]
Default Value
Register Name
PME Device Enable Register
MSB
LSB
30
F0
F1
F2
F3
F4
F5
F6
F8
F9
FA
FC
FE
E0
E1
E2
E3
E4
E5
E6
E7
E8
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
0
-
PME Event Enable 1 Register
PME Event Status 1 Register
PME Event Enable 2 Register
PME Event Status 2 Register
ACPI Control Register 1
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
-
-
0
0
-
0
1
0
0
0
-
0
1
0
0
-
1
1
-
1
-
1
-
ACPI Control Register 2
-
0
-
ACPI Control Register 3
0
-
-
-
LED Control Register 1
0
0
-
0
0
-
0
0
1
-
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
1
0
0
0
-
LED Control Register 2
-
LED Control Register 3
-
0
-
DSW Delay Register
-
-
-
-
RI De-bounce Select Register
ERP Enable Register
0
-
0-
-
-
-
-
-
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
ERP Control Register 1
1
-
0
0
0
0
1
0
1
-
ERP Control Register 2
0
1
1
1
1
1
0
ERP PWSIN De-bounce Register
ERP RSMRST De-bounce Register
ERP PWSOUT Pulse Register
ERP PSON De-bounce Register
ERP Deep S5 Delay Register
ERP Wakeup Enable Register
0
0
1
0
0
0
176
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
