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F81867D 参数 Datasheet PDF下载

F81867D图片预览
型号: F81867D
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART μSuper IO 128字节FIFO和省电功能 [6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions]
分类和应用: 先进先出芯片
文件页数/大小: 315 页 / 2394 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81867  
0: Disable SMI event.  
1
0
GPIO51_SMI_EN  
GPIO50_SMI_EN  
R/W LRESET#  
R/W LRESET#  
0
0
1: Enable SMI event via PME# or SIRQ if GPIO51_SMI_ST is set.  
0: Disable SMI event.  
1: Enable SMI event via PME# or SIRQ if GPIO50_SMI_ST is set.  
GPIO5 SMI Status Register Index A9h  
Bit  
Name  
R/W Reset Default  
Description  
0: No SMI event.  
7
GPIO57_SMI_ST  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
R/W LRESET#  
0
0
0
0
0
0
0
0
1: A SMI event will set if GPIO57 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
6
5
4
3
2
1
0
GPIO56_SMI_ST  
GPIO55_SMI_ST  
GPIO54_SMI_ST  
GPIO53_SMI_ST  
GPIO52_SMI_ST  
GPIO51_SMI_ST  
GPIO50_SMI_ST  
1: A SMI event will set if GPIO56 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO55 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO54 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO53 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO52 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO51 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
0: No SMI event.  
1: A SMI event will set if GPIO50 input is changed.  
This bit is available in input mode. Write “1” to this bit will clear the status.  
7.7.10 GPIO6x Configuration Registers  
Register  
0x[HEX]  
Default Value  
Register Name  
MSB  
LSB  
90  
GPIO6 Output Enable Register  
GPIO6 Output Data Register  
GPIO6 Pin Status Register  
GPIO6 Drive Enable Register  
0
0
1
-
0
1
-
0
1
-
0
1
-
0
0
1
-
0
1
-
91  
92  
93  
1
-
1
-
0
0
0
0
0
0
0
0
162  
Dec, 2011  
V0.12P  
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