F81867
7.1.9 Port Select Register ⎯ Index 27h
Bit
Name
R/W Reset Default
Description
0: Enable OVP function.
7
OVP_MODE
R/W VBAT*
R/W 5VSB
-
1: Default is disabled; internal pull high 47k Ω .
The default value is determined by power on strap.
0: ATX Mode.
6
5
AT_MODE
-
1: AT Mode.
The default value is determined by power on strap.
0: The GPIO I/O space is 8-byte.
1: The GPIO I/O space is 16-byte.
GPIO_DEC_RANGE R/W 3VCC
0
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
4
PORT_4E_EN
R/W 5VSB*
-
This register is power on trapped by RTS1#/ Config4E_2E. Pull down to select
port 2E/2F. This bit is accessed by the host side only.
Index 0x2C register select.
00: GPIO0_EN
3-2
GPIO_PROG_SEL R/W 5VSB
0
01: GPIO1_EN
10: GPIO2_EN
11: μC_PORT_EN.
Host set this bit “1” to stop μC.
1
0
HOST_STOP_μC
R/W
-
0
0
To enter debug mode, host should stop this bit first.
This bit is accessed by host side only.
CLK_TUNE_PROG_
EN
Set “1” to enable index 0x29, 0x2A, 0x2B, 0x2C function as clock fine tune
register.
R/W 3VCC
7.1.10Multi-function Select 1 Register ⎯ Index 28h (Available when GPIO_PROG_SEL[0] = 0)
Bit
Name
R/W
Default
Description
Reset
7
Reserved
-
-
-
Reserved
Pin 9 ~ 21 function select.
These pins are controlled by FDC_GP_EN, UART5_FUNC_SEL, and
UART6_FUNC_SEL.
6
FDC_GP_EN
R/W 5VSB
1
If all these bits are clear to “0”, the function would be FDC.
Pin 102 ~ 118 function select.
0: Functions as parallel port.
1: Functions as GPIO7x/GPIO8x.
5
4
LPT_GP_EN
MO_ I2C _EN
R/W 5VSB
R/W 5VSB
1
0
Pin 61, 62 function select.
0: PS/2 mouse interface MCLK/MDATA.
1: I2C SCL/SDA.
UART 5 Function Select.
00: No UART 5 pin.
01: Simple UART, only SIN5 and SOUT5 are available. Pin 57 will be function
as SOUT5 and Pin 58 will be function as SIN5.
3-2 UART5_FUNC_SEL R/W 5VSB
0
10: Simple UART with RTS#. Pin 59 will be function as RTS5#.
11: Full UART, pin 57 ~ 59, 17 ~ 21 will function as UART 5 pins.
122
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
