F81867
7.1.1510Hz Clock Divisor Low Byte ⎯ Index 2Ah (Available when CLK_TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
The divisor of 10Hz clock. Internal 10Hz clock is used to generate WDT
event. It is divided from 10KHz clock and could be fine tune by change its
divisor.
7-0
CLK10HZ_DIV
R/W
8’hE7
VBAT
7.1.16Multi Function Select 4 Register ⎯ Index 2Bh (Available when CLK_ TUNE_PROG_EN = 0)
Bit
Name
R/W Reset Default
Description
Pin 87 function select
7
6
GPIO67_EN
R/W
0
0
VBAT
0: Pin 87 functions as S5#.
1: Pin 87 functions as GPIO67.
Pin 86 function select
GPIO66_EN
R/W VBAT
R/W VBAT
0: Pin 86 functions as DPWROK.
1: Pin 86 functions as GPIO66.
Pin 74 function select
5
4-2
1
GPIO65_EN
Reserved
0
-
0: Pin 74 functions as PME#.
1: Pin 74 functions as GPIO65.
-
-
Reserved
Pin 102 function select
FANIN3_EN
R/W VBAT
R/W VBAT
1
0: Pin 102 functions as SCLT.
1: Pin 102 functions as FANIN3.
Pin 103 function select.
0
FANCTRL3_EN
0
0: Pin 103 functions as GPIO70/PE.
1: Pin 103 functions as FANCTRL3.
7.1.1710Hz Clock Fine Tune Count High Byte ⎯ Index 2Bh (Available when CLK_ TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
This bit indicates the fine tune mechanism is in process.
Reserved
7
FINE_TUNE_ST
-
-
-
-
5VSB
-
6-4
3-0
Reserved
FINE_TUNE_CNT R/W 5VSB
4’h3
This is the count of 10 cycles of internal 500KHz clock with 48MHz clock.
7.1.1810Hz Clock Fine Tune Count Low Byte ⎯ Index 2Ch (Available when CLK_ TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
4’h3
Description
7-0
FINE_TUNE_CNT R/W
5VSB
This is the count of 10 cycles of internal 500KHz clock with 48MHz clock.
125
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
