F81866A
0: No SMI event.
6
5
4
3
2
1
0
GPIO86_SMI_ST
GPIO85_SMI_ST
GPIO84_SMI_ST
GPIO83_SMI_ST
GPIO82_SMI_ST
GPIO81_SMI_ST
GPIO80_SMI_ST
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
0
0
0
0
0
0
0
1: A SMI event will set if GPIO86 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO85 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO84 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO83 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO82 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO81 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO80 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
Remark:
GPIO also provides index/data port to access the whole GPIO registers. The index port is base address + 0 and
data port is base address + 1. The index for each register is the same as the one for configuration register. For
example, to write GPIO0 output enable register 0xAA, below is the procedure:
1. Write index port 0xF0.
2. Write data port 0xAA.
7.8 WDT Device Configuration Registers (LDN CR07)
“-“ Reserved or Tri-State
Default Value
Register 0x[HEX]
Register Name
WDT Device Enable Register
MSB
LSB
30
60
61
F5
F6
FA
-
-
-
-
-
-
0
0
0
0
-
-
0
0
0
0
0
0
Base Address High Register
Base Address Low Register
WDT Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
-
WDT Timer Register
WDT PME Enable Register
1
7.8.1WDT Device Base Address Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
0
Reserved
0: disable WDT base address.
1: enable WDT base address.
0
WDT_EN
R/W 5VSB
0
166
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
