F81866A
0: Disable SMI event.
4
3
2
1
0
GPIO54_SMI_EN
GPIO53_SMI_EN
GPIO52_SMI_EN
GPIO51_SMI_EN
GPIO50_SMI_EN
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
0
0
0
0
0
1: Enable SMI event via PME# or SIRQ if GPIO54_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO53_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO52_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO51_SMI_ST is set.
0: Disable SMI event.
1: Enable SMI event via PME# or SIRQ if GPIO50_SMI_ST is set.
7.7.9.6GPIO5 SMI Status Register ⎯ Index A9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7
GPIO57_SMI_ST
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
0
0
0
0
0
0
0
0
1: A SMI event will set if GPIO57 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6
5
4
3
2
1
0
GPIO56_SMI_ST
GPIO55_SMI_ST
GPIO54_SMI_ST
GPIO53_SMI_ST
GPIO52_SMI_ST
GPIO51_SMI_ST
GPIO50_SMI_ST
1: A SMI event will set if GPIO56 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO55 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO54 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO53 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO52 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO51 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1: A SMI event will set if GPIO50 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
7.7.10.GPIO6x Configuration Registers
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
90
GPIO6 Output Enable Register
GPIO6 Output Data Register
GPIO6 Pin Status Register
0
0
1
-
0
1
-
0
1
-
0
1
-
0
0
1
-
0
1
-
91
92
1
-
1
-
159
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
