F81866A
5-3
2
Reserved
CLRTX
-
LRESET#
LRESET#
LRESET#
-
Reserved.
Reset the transmitter FIFO.
R
R
0
0
Reset the receiver FIFO.
1
CLRRX
0: Disable FIFO.
1: Enable FIFO.
0
FIFO_EN
R
LRESET#
0
Line Control Register (LCR) ⎯ Base + 3
Bit
Name
R/W Reset Default
Description
0: Divisor Latch can’t be accessed.
1: Divisor Latch can be accessed via Base and Base+1.
0: Transmitter is in normal condition.
1: Transmit a break condition.
XX0: Parity Bit is disable
7
DLAB
R/W LRESET#
R/W LRESET#
0
0
6
SETBRK
5
4
STKPAR
EPS
R/W LRESET#
R/W LRESET#
0
0
001: Parity Bit is odd.
011: Parity Bit is even
101: Parity Bit is logic 1
111: Parity Bit is logic 0
3
2
PEN
STB
R/W LRESET#
R/W LRESET#
0
0
0: Stop bit is one bit
1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
00: Word length is 5 bit
01: Word length is 6 bit
10: Word length is 7 bit
1-0
WLS
R/W LRESET#
00
11: Word length is 8 bit
MODEM Control Register (MCR) ⎯ Base + 4
Bit
Name
R/W Reset Default
Description
Reserved.
7-5
Reserved
-
LRESET#
-
0: UART in normal condition.
1: UART is internal loop back
0: All interrupt is disabled.
1: Interrupt is enabled (disabled) by IER.
Read from MSR[6] while in loop back mode
4
LOOP
R/W LRESET#
0
3
2
1
OUT2
OUT1
RTS
R/W LRESET#
R/W LRESET#
R/W LRESET#
0
0
0
0: RTS# is forced to logic 1
1: RTS# is forced to logic 0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
0
DTR
R/W LRESET#
0
Line Status Register (LSR) ⎯ Base + 5
Bit
Name
R/W Reset Default
Description
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
7
RCR_ERR
R
R
R
R
R
LRESET#
LRESET#
LRESET#
LRESET#
LRESET#
0
1
1
0
0
6
5
4
3
TEMT
THRE
BI
1: Transmitter is empty.
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
1: A break condition is detected.
0: Data received has no frame error.
1: Data received has frame error.
FE
111
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
