F81218
outportb(0x4f, 0x04); //Set Address decoder 1 base address high byte to 0x04
outportb(0x4e, 0x61); //Select LDN 7 register index 0x61
outportb(0x4f, 0x80); //Set Address decoder 1 base address low byte to 0x80
outportb(0x4e, 0x62); //Select LDN 7 register index 0x62
outportb(0x4f, 0x00); //Set Address decoder 0 base address decode A0~A15
outportb(0x4e, 0x30); //Select LDN 7 register index 0x30
outportb(0x4f, 0x01); //Enable Address decoder 1 Device
outportb(0x4e, 0xaa); //Exit configuration mode
4. Set Watch Dog timer base address 0x300~0x301:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77); //Entry configuration mode
outportb(0x4e, 0x07); //Select register index 0x07
outportb(0x4f, 0x08); //Select LDN 8
outportb(0x4e, 0x60); //Select LDN 8 register index 0x60
outportb(0x4f, 0x03); //Set Watch Dog timer base address high byte to 0x03
outportb(0x4e, 0x61); //Select LDN 8 register index 0x61
outportb(0x4f, 0x00); //Set Watch Dog Timer base address low byte to 0x00
outportb(0x4e, 0x30); //Select LDN 8 register index 0x30
outportb(0x4f, 0x01); //Enable Watch Dog Timer Device
outportb(0x4e, 0xaa); //Exit configuration mode
5. Set Watch Dog timer to 20 second used base address 0x300~0x301:
outportb(0x300, 0x03); //Select unit to one second and clear time out status
outportb(0x301, 0x14);
outportb(0x301, 0x14); //Set timer to 20 second and enable timer
6.1 Global Control Register
6.1.1 Software Reset Register – index 02h
Power-on default [7:0] = 0x00h
Bit
7:1
Name
Reserved
SWRST
R/W
R/W
R/W
Description
Return 0 when read.
0
Write 1 to reset configuration register. This bit is auto cleared.
-23-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
