F75113
9.3.3 SMBus Interface
t
t
SCL
R
t
R
SCL
t
SU;STO
t
t
HD;DAT
HD;SDA
SDA IN
VALID DATA
t
SU;DAT
SDA OUT
Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER
SYMBOL
t-SCL
MIN.
10
MAX.
UNIT
SCL clock period
uS
uS
uS
nS
nS
uS
nS
Start condition hold time
Stop condition setup-up time
DATA to SCL setup time
DATA to SCL hold time
SCL and SDA rise time
SCL and SDA fall time
tHD;SDA
tSU;STO
tSU;DAT
tHD;DAT
tR
4.7
4.7
120
5
1.0
tF
300
9.3.4 SPI Interfcae
tSHSL
/CS
tCHSH
tSHCH
tCHSL
tSLCH
CLK
tCLCH
tCHCL
tDVCH
tCHDX
MSB IN
LSB IN
HMOSI
High Impedance
HMISO
SPI Timing Diagram
- 80 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
