F75113
Typical Timing for Host Read
LCLK
T1
T2
T4
LFRAME#
LAD[3:0]
T3
T5
0110 Sync Data Data PTAR HZ
Start DIR ADDR ADDR ADDR ADDR HTAR HZ
4 or 8
Clocks
2 - 2k
Clocks
0 - i
Clocks
1 - j
Clocks
Host read timing diagram
Typical Timing for Host Write
LCLK
T8
T6
T7
LFRAME#
LAD[3:0]
Start DIR ADDR ADDR ADDR ADDR Data Data HTAR HZ
Sync PTAR HZ
Host write timing diagram
Timing for Aboart Mechanism
LCLK
LFRAME#
LAD[3:0]
Start DIR ADDR ADDR ADDR ADDR HTAR HZ
0110 Sync Sync
4 or 8
Clocks
Peripheral must
stop driving
0 - i
Clocks
Too many Syncs
causes timeout
Host will
drive high
Host abort timing diagram
- 78 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
