F75113
9.3.2 Serialized IRQ Interface
NO.
T1
T2
T3
T4
T5
T6
T7
DESCRIPTION
MIN.
2
MAX.
12
UNIT
nS
Host drive SERIRQ low after rising edge of PCICLK
Host drive SERIRQ high after rising edge of PCICLK
Slave drive SERIRQ low after rising edge of PCICLK
Slave drive SERIRQ high after rising edge of PCICLK
Period of PCICLK
2
12
nS
2
12
nS
2
12
nS
27
12
12
33
nS
Duration of PCICLK low
nS
Duration of PCICLK high
nS
SIRQ interface timing table
Start Frame Timing
Start Frame
H
IRQ0 Frame
R
IRQ1 Frame
R
IRQ2 Frame
R
SL
or
H
R
S
S
S
T
T
T
T
PCICLK
T1
T3
T4
T2
Start
SERIRQ
Drive
4 - 8 Clocks
IRQ1
Host Controller
None
IRQ1
None
Source
H : Host Control SL : Slave Control R : Recovery T : Turn-around S : Sample
SIRQ start frame timing diagram
Stop Frame Timing
IRQ14 Frame
IRQ15 Frame
IOCHCK# Frame
Stop Frame
H R
Next Cycle
S
R
S
R
S
R
T
T
T
I
T
PCICLK
SERIRQ
T7
T5
T6
T1
T2
Stop
0 - n
Clocks
2 or 3 Clocks
Drive
Source
None
IRQ15
None
Host Controller
H : Host Control SL : Slave Control R : Recovery T : Turn-around S : Sample I : Idle
SIRQ stop frame timing diagram
- 79 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
