F75113
Indicate GPIO45 Edge Status. If set to 1, the edge of GPIO45
5
4
3
2
1
0
STS_GP45EDGE
STS_GP44EDGE
STS_GP43EDGE
STS_GP42EDGE
STS_GP41EDGE
STS_GP40EDGE
R
R
R
R
R
R
-
-
-
-
-
-
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO44 Edge Status. If set to 1, the edge of GPIO44
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO43 Edge Status. If set to 1, the edge of GPIO43
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO42 Edge Status. If set to 1, the edge of GPIO42
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO41 Edge Status. If set to 1, the edge of GPIO41
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO40 Edge Status. If set to 1, the edge of GPIO40
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
8.2.41 GPIO4X SMI Enable Register ⎯ Index 7Ah
Bit
Name
R/W Default
Description
Enable GPIO47 SMI Generation. If this bit set to 1, enable
GPIO47 to generate SMI.
7
EN_GP47SMI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Enable GPIO46 SMI Generation. If this bit set to 1, enable
GPIO46 to generate SMI.
6
5
4
3
2
1
0
EN_GP46SMI
EN_GP45SMI
EN_GP44SMI
EN_GP43SMI
EN_GP42SMI
EN_GP41SMI
EN_GP40SMI
Enable GPIO45 SMI Generation. If this bit set to 1, enable
GPIO45 to generate SMI.
Enable GPIO44 SMI Generation. If this bit set to 1, enable
GPIO44 to generate SMI.
Enable GPIO43 SMI Generation. If this bit set to 1, enable
GPIO43 to generate SMI.
Enable GPIO42 SMI Generation. If this bit set to 1, enable
GPIO42 to generate SMI.
Enable GPIO41 SMI Generation. If this bit set to 1, enable
GPIO41 to generate SMI.
Enable GPIO40 SMI Generation. If this bit set to 1, enable
GPIO40 to generate SMI.
- 73 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
