F75113
Indicate GPIO05 Edge Status. If set to 1, the edge of GPIO05
5
4
3
2
1
0
STS_GP05EDGE
STS_GP04EDGE
STS_GP03EDGE
STS_GP02EDGE
STS_GP01EDGE
STS_GP00EDGE
R
R
R
R
R
R
-
-
-
-
-
-
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO04 Edge Status. If set to 1, the edge of GPIO04
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO03 Edge Status. If set to 1, the edge of GPIO03
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO02 Edge Status. If set to 1, the edge of GPIO02
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO01 Edge Status. If set to 1, the edge of GPIO01
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO00 Edge Status. If set to 1, the edge of GPIO00
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
8.2.22 GPIO0X SMI Enable Register ⎯ Index 1Ah
Bit
Name
R/W Default
Description
Enable GPIO07 SMI Generation. If this bit set to 1, enable
GPIO07 to generate SMI.
7
EN_GP07SMI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Enable GPIO06 SMI Generation. If this bit set to 1, enable
GPIO06 to generate SMI.
6
5
4
3
2
1
0
EN_GP06SMI
EN_GP05SMI
EN_GP04SMI
EN_GP03SMI
EN_GP02SMI
EN_GP01SMI
EN_GP00SMI
Enable GPIO05 SMI Generation. If this bit set to 1, enable
GPIO05 to generate SMI.
Enable GPIO04 SMI Generation. If this bit set to 1, enable
GPIO04 to generate SMI.
Enable GPIO03 SMI Generation. If this bit set to 1, enable
GPIO03 to generate SMI.
Enable GPIO02 SMI Generation. If this bit set to 1, enable
GPIO02 to generate SMI.
Enable GPIO01 SMI Generation. If this bit set to 1, enable
GPIO01 to generate SMI.
Enable GPIO00 SMI Generation. If this bit set to 1, enable
GPIO00 to generate SMI.
- 32 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
