F75113
8.2.14 GPIO0X Input Status Register ⎯ Index 12h
Bit
7
Name
R/W Default
Description
Read the GPIO07 data on the pin.
GP07_ PSTS
GP06_ PSTS
GP05_ PSTS
GP04_ PSTS
GP03_ PSTS
GP02_ PSTS
GP01_ PSTS
GP00_PSTS
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
6
Read the GPIO06 data on the pin.
Read the GPIO05 data on the pin.
Read the GPIO04 data on the pin.
Read the GPIO03 data on the pin.
Read the GPIO02 data on the pin.
Read the GPIO01 data on the pin.
Read the GPIO00 data on the pin.
5
4
3
2
1
0
8.2.15 GPIO0X Level/Pulse Control Register ⎯ Index 13h
Name R/W Default
Bit
7
Description
GPIO07 output mode. 0 – level, 1 – pulse.
GPIO06 output mode. 0 – level, 1 – pulse.
GPIO05 output mode. 0 – level, 1 – pulse.
GPIO04 output mode. 0 – level, 1 – pulse.
GPIO03 output mode. 0 – level, 1 – pulse.
GPIO02 output mode. 0 – level, 1 – pulse.
GPIO01 output mode. 0 – level, 1 – pulse.
GPIO00 output mode. 0 – level, 1 – pulse.
GP07_ OMODE R/W
GP06_ OMODE R/W
GP05_ OMODE R/W
GP04_ OMODE R/W
GP03_ OMODE R/W
GP02_ OMODE R/W
GP01_ OMODE R/W
GP00_ OMODE R/W
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
8.2.16 GPIO0X Pulse Width Control Register ⎯ Index 14h
Bit
Name
R/W Default
Description
7-2
Reserved
-
-
Reserved
GPIO0X pulse width. If set the GPIO0X to pulse mode, the pulse
width can be defined as follows.
00b – 500us (Default)
01b – 1ms
1-0
GP0_PLSWD
R/W
0
10b – 20ms
11b – 100ms
- 28 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
