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F71872FG 参数 Datasheet PDF下载

F71872FG图片预览
型号: F71872FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级H / W监控+ LPC IO [Super H/W Monitor + LPC IO]
分类和应用: 监控PC
文件页数/大小: 115 页 / 3055 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71872  
0
3VDD_RT  
R
0
A one indicates 3VDD is at abnormal range.  
7.6.3.19 REAL_TIME STATUS Register 2 Index 37h  
Bit  
Name  
R/W Default  
Description  
7-6 Reserved  
-
-
5
4
3
2
1
0
T3_RT  
R
R
R
R
R
R
0
0
0
0
0
0
A one indicates T3 exceeds its high limit.  
T2_RT  
A one indicates T2 exceeds its high limit.  
A one indicates VBAT exceeds its high limit.  
T1_RT  
A one indicates VBAT exceeds its high limit.  
VBAT_RT  
VSB_RT  
VIN8_RT  
A one indicates VSB exceeds its high limit.  
A one indicates VIN8 exceeds its high limit.  
7.6.3.20 REAL_TIME STATUS Register 3 Index 38h  
Bit  
Name  
R/W Default  
Description  
7
6
5
Reserved  
-
-
CASEOPEN  
R
R
0
0
A one indicates that chassis is opened.  
A one indicates FAN3 can not reach the expect count in time when FANPWM3  
duty-cycle is 100%. The time is defined by FAN3 Fault Time registers. After  
FAN3 reaches the expect count, the bit will be set to 0.  
FAN3_TAR_RT  
A one indicates FAN2 can not reach the expect count in time when FANPWM2  
duty-cycle is 100%. The time is defined by FAN2 Fault Time registers. After  
FAN2 reaches the expect count, the bit will be set to 0.  
A one indicates FAN1 can not reach the expect count in time when FANPWM1  
duty-cycle is 100%. The time is defined by FAN1 Fault Time registers. After  
FAN1 reaches the expect count, the bit will be set to 0.  
4
3
FAN2_TAR_RT  
FAN1_TAR_RT  
R
R
0
0
A one indicates FAN3 is at abnormal range.  
2
1
0
FAN3_RT  
FAN2_RT  
FAN1_RT  
R
R
R
0
0
0
A one indicates FAN2 is at abnormal range.  
A one indicates FAN1 is at abnormal range.  
7.6.3.21 VIN_FAULT Mode Register 3 Index 39h  
Bit  
Name  
R/W Default  
Description  
7
VIN7F_SEL  
R/W  
0
Set to 1, VIN7_ID value will not change until REG 3Ah Bit7 is cleared if that bit  
is set. Set to 0, Reserved.  
6-4 Reserved  
-
-
Set to 1, once VIN4_FAULT is asserted, it will not be de-asserted when VIN4 is  
back to normal range.  
3
VIN4F_SEL  
R
0
Set to 0, VIN4_FAULT is asserted/de-asserted according to its value whether is  
out of high/low limit.  
Set to 1, once VIN3_FAULT is asserted, it will not be de-asserted when VIN4 is  
back to normal range.  
2
VIN3F_SEL  
R
0
Set to 0, VIN3_FAULT is asserted/de-asserted according to its value whether is  
out of high/low limit.  
75  
July, 2007  
V0.28P  
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