F71872
7.6.3.13 INTERRUPT ENABLE Control Register 2 Index 31h
Bit
Name
R/W Default
Description
7-6 Reserved
-
-
5
4
3
2
1
0
EN_T3
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Set to 1, enables T3 abnormal interrupt.
EN_T2
Set to 1, enables T2 abnormal interrupt.
Set to 1, enables T1 abnormal interrupt.
Set to 1, enables VBAT abnormal interrupt.
Set to 1, enables VSB abnormal interrupt.
Set to 1, enables VIN8 abnormal interrupt.
EN_T1
EN_VBAT
EN_VSB
EN_VIN8
7.6.3.14 INTERRUPT ENABLE Control Register 3 Index 32h
Bit
Name
R/W Default
Description
7
6
5
Reserved
-
-
EN_CASE
R/W
R/W
0
0
Set to 1, enables Chassis Open interrupt.
EN_FAN3_TAR
Set to 1, enables FAN3 target speed mismatched interrupt when FANPWM3
duty-cycle is 100%.
4
3
EN_FAN2_TAR
EN_FAN1_TAR
R/W
R/W
0
0
Set to 1, enables FAN2 target speed mismatched interrupt when FANPWM2
duty-cycle is 100%.
Set to 1, enables FAN1 target speed mismatched interrupt when FANPWM1
duty-cycle is 100%.
Set to 1, enables FAN3 abnormal interrupt.
2
1
0
EN_FAN3_LMT
EN_FAN2_LMT
EN_FAN1_LMT
R/W
R/W
R/W
0
0
0
Set to 1, enables FAN2 abnormal interrupt.
Set to 1, enables FAN1 abnormal interrupt.
7.6.3.15 INTERRUPT STATUS Register 1 Index 33h
Bit
Name
R/W Default
Description
7
VIN7_STS
R/W
R/W
R/W
R/W
0
0
0
0
A one indicates VIN7 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
6
5
4
VIN6_STS
VIN5_STS
VIN4_STS
A one indicates VIN6 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
A one indicates VIN5 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
A one indicates VIN4 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
A one indicates VIN3 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
A one indicates VIN2 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
A one indicates VIN1 reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
3
2
1
VIN3_STS
VIN2_STS
VIN1_STS
R/W
R/W
R/W
0
0
0
0
3VDD_STS
R/W
0
A one indicates 3VDD reaches its high or low limit. Write 1 to clear this bit,
write 0 will be ignored.
73
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
