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F71872FG 参数 Datasheet PDF下载

F71872FG图片预览
型号: F71872FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级H / W监控+ LPC IO [Super H/W Monitor + LPC IO]
分类和应用: 监控PC
文件页数/大小: 115 页 / 3055 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71872  
7-5 ECP_MODE  
R/W  
000 000: SPP Mode.  
001: PS/2 Parallel Port Mode.  
010: Parallel Port Data FIFO Mode.  
011: ECP Parallel Port Mode.  
100: EPP Mode.  
101: Reserved.  
110: Test Mode.  
111: Configuration Mode.  
Only valid in ECP.  
4
3
2
ERRINTR_EN  
DAMEN  
R/W  
R/W  
R/W  
0
0
1
0: disable the interrupt generated on the falling edge of ERR#.  
1: enable the interrupt generated on the falling edge of ERR#.  
0: disable DMA.  
1: enable DMA. DMA starts when SERVICEINTR is 0.  
SERVICEINTR  
0: enable the following case of interrupt.  
DMAEN = 1: DMA mode.  
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more  
bytes are free in the FIFO.  
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more  
bytes are valid to be read in the FIFO.  
1
0
FIFOFULL  
R
R
0
0
0: The FIFO has at least 1 free byte.  
1: The FIFO is completely full.  
FIFOEMPTY  
0: The FIFO contains at least 1 byte.  
1: The FIFO is completely empty.  
7.6 Hardware Monitor Registers  
7.6.1 Logic Device Number Register  
Logic Device Number Register Index 07H  
Bit  
Name  
R/W Default  
Description  
67  
July, 2007  
V0.28P  
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