F71872
7.5.3.5 EPP Address Register Base + 3
Bit
Name
R/W Default
Description
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Address Write protocol.
7-0 EPP_ADDR
R/W
00h
Read this register will cause the hardware to auto receive data from the device
by with the EPP Address Read protocol.
7.5.3.6 EPP Data Register Base + 4 – Base + 7
Bit
Name
R/W Default
Description
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Data Write protocol.
7-0 EPP_DATA
R/W
00h
Read this register will cause the hardware to auto receive data from the device
by with the EPP Data Read protocol.
7.5.3.7 Parallel Port Data FIFO Base + 400h
Bit
Name
R/W Default
Description
7-0 C_FIFO
R/W
00h Data written to this FIFO is auto transmitted by the hardware to the device by
using standard parallel port protocol.
It is only valid in ECP and the ECP_MODE is 010b.The operation is only for
forward direction.
7.5.3.8 ECP Data FIFO Base + 400h
Bit
Name
R/W Default
Description
7-0 ECP_DFIFO
R/W
00h Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to
the device by using ECP parallel port protocol.
Data is auto read from device into the FIFO when DIR is 1 by the hardware by
using ECP parallel port protocol. Read the FIFO will return the content to the
system.
It is only valid in ECP and the ECP_MODE is 011b.
7.5.3.9 ECP Test FIFO Base + 400h
Bit
Name
R/W Default
Description
7-0 T_FIFO
R/W
00h Data may be read, written from system to the FIFO in any Direction. But no
hardware handshake occurred on the parallel port lines. It could be used to test
the empty, full and threshold of the FIFO.
It is only valid in ECP and the ECP_MODE is 110b.
7.5.3.10 ECP Configuration Register A Base + 400h
Bit
Name
R/W Default
Description
65
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
