F71862
Temperature Real Time Status Register Index 62h
Bit
Name
R/W Default
Description
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is
below the “OVT limit –hysteresis” temperature.
0
7
T3_OVT
R/W
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is
below the “OVT limit –hysteresis” temperature.
0
6
T2_OVT
R/W
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is
below the “OVT limit –hysteresis” temperature.
Reserved
0
5
4
3
T1_OVT
Reserved
T3_EXC
R/W
R/W
R/W
0
0
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is
below the “high limit –hysteresis” temperature.
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is
0
0
0
2
T2_EXC
R/W
below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is
below the “high limit –hysteresis” temperature.
Reserved
1
0
T1_EXC
R/W
R/W
Reserved
Temperature BEEP Enable Register Index 63h
Bit
Name
R/W Default
Description
EN_ T3_OVT_BEEP
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT
limit setting.
0
7
R/W
R/W
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
0
0
6
EN_ T2_ OVT_BEEP
EN_ T1_ OVT_BEEP
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
limit setting.
Reserved
5
4
3
R/W
R/W
Reserved
0
0
EN_ T3_EXC_BEEP
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
limit setting.
Reserved
R/W
R/W
0
0
0
2
EN_ T2_EXC_BEEP
EN_ T1_EXC_BEEP
1
0
R/W
R/W
Reserved
OVT Output Enable Register 1 Index 66h
Bit
Name
R/W Default
Description
Enable temperature 3 alert event (asserted when temperature over high
limit)
0
7
EN_T3_ALERT
R
Enable temperature 2 alert event (asserted when temperature over high
0
6
5
EN_T2_ALERT
EN_T1_ALERT
R
limit)
Enable temperature 1 alert event (asserted when temperature over high
limit)
0
R
Reserved for temp4
4
3
2
1
0
Reserved
EN_T3_OVT
EN_T2_OVT
EN_T1_OVT
Reserved
R
0
0
Enable over temperature (OVT) mechanism of temperature3.
Enable over temperature (OVT) mechanism of temperature2.
Enable over temperature (OVT) mechanism of temperature1.
Reserved.
R/W
R/W
R/W
R
0
1
0h
53
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
