F71869A
0: Default Invert signal
1: Invert disable
7
6
LED_INV_DIS
R/W
0
0
0: Disable LED_VCC deep S3 mode.
1: Enable LED_VCC deep S3 mode. LED_VCC will output 0.25Hz
clock with 75% duty when enter deep S3 state.
LED_VCC_DS3 R/W
Select LED_VCC mode in S5 state. The mode is controlled by
{LED_VCC_S5_ADD, LED_VCC_S5_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
LED_VCC_S5_MO
5-4
3-2
1-0
R/W
DE
0
0
0
Select LED_VCC mode in S3 state. The mode is controlled by
{LED_VCC_S3_ADD, LED_VCC_S3_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
LED_VCC_S3_MO
R/W
DE
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
Select LED_VCC mode in S0 state. The mode is controlled by
{LED_VCC_S0_ADD, LED_VCC_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
LED_VCC_S0_MO
R/W
DE
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
6.11.24 LED VSB Mode Select Register ⎯ Index F9h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved
0: Disable LED_VSB deep S3 mode.
6
LED_VSB_DS3 R/W
0
1: Enable LED_VSB deep S3 mode. LED_VSB will output 0.25Hz
clock with 25% duty when enter deep S3 state.
140
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
