F71869A
Select LED_VCC mode in S0 state. The mode is controlled by
{LED_VCC_S0_ADD, LED_VCC_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
LED_VCC_S0_AD
D
0
R/W
0
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
6.11.26 Intel DSW Delay Select Register ⎯ Index FCh
Bit
7-4
3-0
Name
R/W Default
Description
Reserved
R/W
R/W
-
Reserved
This is the delay time for SUS_ACK# and SUS_WARN#. Time unit is 0.5s.
DSW_DELAY
7h
6.11.27 RI De-bounce Select Register ⎯ Index FEh
Bit
7
Name
R/W Default
Description
After entry key is enabled, write “1” to enable trim operation.
Enable CRFD for entry data.
Reserved
WR_TRIM_EN
WR_KEY_EN
Reserved
R/W
R/W
-
0
0
-
6
5
4
CIR_VDD_S3
Reserved
R/W
-
0
-
Write “1” to emulate a S3 state for CIR.
Reserved
3-2
Select RI de-bounce time.
00: reserved.
01: 200us.
1-0
RI_DB_SEL
R/W
0
10: 2ms.
11: 20ms.
143
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
