F71869A
This registers companying with FAN3_TEMP_SEL_DIG select the
temperature source for controlling FAN3. The following value is
comprised by {FAN3_TEMP_SEL_DIG, FAN3_TEMP_SEL}
000: fan3 follows PECI temperature (CR7Eh)
001: fan3 follows temperature 1 (CR72h).
010: fan3 follows temperature 2 (CR74h).
1-0
FAN3_TEMP_SEL R/W
11
011: fan3 follows temperature 3 (CR76h).
100: fan3 follows IBEX/TSI CPU temperature (CR7Ah)
101: fan3 follows IBEX PCH temperature (CR7Bh).
110: fan3 follows IBEX MCH temperature (CR7Ch).
111: fan3 follows IBEX maximum temperature (CR7Dh).
Otherwise: reserved.
6.6.98 TSI Temperature 0 – Index E0h
Bit
Name
R/W Default
Description
This is the AMD TSI reading if AMD TSI enable.
And will be highest temperature among CPU, MCH and PCH if Intel
temperature interface enable. The range is 0~255’C. To access this
byte, MCH_BANK_SEL must set to “0”.
TSI_TEMP0
R/W
-
This byte is used as multi-purpose:
1. The received data of receive protocol.
7-0
2. The first received byte of read word protocol.
3. The 10th received byte of read block protocol.
4. The sent data for send byte protocol and write byte protocol.
5. The first send byte for write word protocol.
6. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
SMB_DATA0
R/W 8’h00
6.6.99 TSI Temperature 1 – Index E1h
Bit
Name
R/W Default
Description
This is the high byte of Intel temperature interface PCH reading. The
range is 0~255’C.
7-0
TSI_TEMP1
R
-
To access this byte, MCH_BANK_SEL should be set to “0”.
106
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
