F71869A
This is the 18th byte of the block read protocol.
7-0
SMB_DATA9
R/W
FFh This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.108
Bit
Block Write Count Register – Index ECh
Name R/W Default
MCH_BANK_SEL R/W
Reserved
BLOCK_WR_CNT R/W
Description
This bit is used to select the register in index E0h to E9h.
Set “0” to read the temperature bank and “1” to access the data bank.
Reserved
7
6
0
0
0
-
Use the register to specify the byte count of block write protocol.
Support up to 10 bytes.
5-0
6.6.109
Bit
SMB Command Byte/TSI Command Byte – Index EDh
Name
R/W Default
Description
There are actual two bytes for this index. TSI_CMD_PROG select
which byte to be programmed:
0: SMB_CMD, which is the command code for write byte/word, read
0/1 byte/word, block write/read and process call protocol.
1: TSI_CMD, which is the command code for Intel temperature
interface block read protocol and the data byte for AMD TSI send byte
protocol.
7-0 SMB_CMD/TSI_CMD R/W
6.6.110
Bit
SMB Status – Index EEh
Name
R/W Default
Description
Set 1 to pending auto TSI accessing. (In AMD model, auto accessing
will issue a send-byte followed a receive-byte; In Intel model, auto
accessing will issue a block read).
7
TSI_PENDING
R/W
0
To use the SCL/ SDA as a SMBus master, set this bit to “1” first.
Set 1 to program TSI_CMD.
6
5
TSI_CMD_PROG R/W
0
0
Kill the current SMBus transfer and return the state machine to idle. It
will set an fail status if the current transfer is not completed.
This is set when PROC_KI LL kill an un-completed transfer. It will be
auto cleared by next SMBus transfer.
PROC_KILL
FAIL_STS
R/W
R
4
3
2
0
0
0
This is the arbitration lost status if a SMBus command is issued. Auto
cleared by next SMBus command.
SMB_ABT_ERR
SMB_TO_ERR
R
This is the timeout status if a SMBus command is issued. Auto
cleared by next SMBus command.
R
109
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
