MC81F4x16
24.1 Registers
UCONH
UART CONTROL HIGH REGISTER (UCONH)
00FCH
When current mode is 2 or 3, and the „MCE‟ bit is enabled, Rx interrupt is generated when only 9th bit
of Rx data is „1‟. This feature is used to Multiprocessor Communication. See „24.4 Muti-processor
Communication‟ on page 158 for more detail information.
In mode 1, and the „MCE‟ bit is enabled, Rx interrupt is generated when only valid stop bit is received.
In mode 0, the „MCE‟ bit must be „0‟.
TB8 and RB8 bits are ignored when current mode is 0 or 1, or the „UTP(UCONL.7 / UART parity auto-
generation)‟ bit is enabled.
7
6
5
4
3
2
1
0
UMS1 UMS0
R/W R/W
MCE
SDR
TB8
RB8
–
–
UCONH
Reset value: 00H
R/W
R/W
R/W
R/W
–
–
00: Mode 0; Synchronous mode
(fu/(16×(BRDAT+1)))
01: Mode 1; 8-bit UART
(fu/(16×(BRDAT+1)))
UMS
UART Mode Selection Bits
10: Mode 2; 9-bit UART
(fxx/16)
11: Mode 3; 9-bit UART
(fu/(16×(BRDAT+1)))
0: Disable
Multiprocessor Communication Enable Bit
(for modes 2 and 3 only)
MCE
SDR
TB8
1: Enable
0: Receive Disable
1: Receive Enable
Serial Data Receive Enable Bit
TB8
9th bit of Tx Data
RB8
RB8
9th bit of Rx Data
–
bit1 – bit0
Not used for MC81F4x32
Note : „fu‟ is the clock source which is selected by the UCLK(UCONL.[2-3]) bits.
150
October 19, 2009 Ver.1.35
FINECHIPS [ FINECHIPS ]
