MC81F4432
20. High Speed PWM
fxx/1024
fxx/256
fxx/64
8-Bit Up Counter
(Read - only)
Clear
T2CC
fxx/16
2-bit
2-bit
R
Match signal
fxx/8
fxx/4
fxx/2
fxx/1
fxt
M
U
X
T2CR
T2CC
Overflow signal
Match
Match signal
8-Bit Comparator
T2MIE
Timer 2 Match INT enable
EC2
2-bit Timer 2 Buffer Register
T2MIR
Timer 2 Match INT request
Counter stop
T2 Match
Interrupt
PPH,
PPL
T2F
T2CS
2-bit Timer 2 Data Register
T2DR
S
R
Q
Q
Q
M
U
X
PWM2O
PWM3O
PWM4O
2-bit
8-Bit Comparator
POL2
Counter stop
2-bit PWM 2 Buffer Register
S
R
M
U
X
P2DH,
P2DL
2-bit PWM 2 Data Register
POL3
POL4
Counter stop
2-bit
8-Bit Comparator
2-bit
8-Bit Comparator
S
R
M
U
X
2-bit PWM 3 Buffer Register
2-bit PWM 4 Buffer Register
Counter stop
T2CC
Match signal
T2CC
Match signal
2-bit PWM 3 Data Register
2-bit PWM 4 Data Register
P3DH,
P3DL
P4DH,
P4DL
NOTE:
1. When you cleared the POLx and counter stop, PWMxO is high status.
2. When you set the POLx and counter stop, PWMxO is low status.
(x=2, 3, 4)
Figure 20-1 High Speed PWM Block Diagram
The MC81F4x32 has three high speed PWM (Pulse Width Modulation) function which shared with
Timer2.
In PWM mode, the R11/PWM2O, R12/PWM3O, R13/PWM4O pins operate as a 10-bit resolution
PWM output port. For this mode, the R11 of R1CONL, the R12 and the R13 of R1CONM should be
set to alternative function mode.
The period of the PWM output is determined by the T2DR (T2 data Register) and PWMPDR[1:0]
(PWM Period Duty Register) and the duty of the PWM output is determined by the PWM2DR,
PWM3DR, PWM4DR (PWM Data Register) and PWMPDR[7:2] (PWM Period Duty Register).
User can use PWM data by writing the lower 8-bit period value to the T2DR and the higher 2-bit
period value to the PWMPDR[1:0]. And the duty value can be used with the PWM2DR, PWM3DR,
PWM4DR and the PWMPDR[7:2] in the same way.
October 19, 2009 Ver.1.35
135
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