MC81F4x16
Function Description
Interval Timer Mode
A match signal is generated and T2O pins are toggled when the T2CR+T3CR register value equals
the T2DR+T3DR. The match signal generates a timer match interrupt and clears the T2CR and the
T3CR register.
If, for example, you write the value 24H to T2DR, 10H to T3DR and 9FH to T2SCR, the counter will
increment until it reaches 1024H. At this point, the Timer 0 math interrupt request is generated, the
counter value is reset, and counting resumes.
Capture Mode
In capture mode, you have to set EXT5 interrupt. When the EXT5 interrupt is occurred, the T2CR and
T2CR register value is loaded into the T2DR and T3DR register and the T2CR and T3CR register is
cleared.
And the timer 2 overflow interrupt is generated whenever the T2CR+T3CR value is overflowed.
So, If you count how many overflow is occurred and read the T2DR+T3DR value in EXT5 interrupt
routine, it is possible to measure the time between two EXT5 interrupts. Or it is possible to measure
the time from the T2 initial time to the EXT5 interrupt occurred time.
The time = (65536* tCLK ) * overflow_count + (tCLK * (T2CR+(T3DR<<8)))
Note
„t ‟ is the period time of the timer-counter‟s clock source
CLK
You must set the T2DR and T3DR values before set the T2SCR register. Because T2DR
and T3DR values are fetched when the count is started(the T2CC bit is set) or
match/overflow event is occurred.
134
October 19, 2009 Ver.1.35
FINECHIPS [ FINECHIPS ]
