CMS4A16LAx–75Ex
Table 11. Current State Bank n, Command to Bank m[68.69.70.71.72.73.]
.
Current State
CS#
RAS#
CAS#
WE#
Command(Action)
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
ACTIVE (Select and activate row)
Read
READ (Select column and start new READ burst)[74.75.81.]
WRITE (Select column and start WRITE burst)[74.75.82.]
PRECHARGE[76.]
(With Auto
Precharge)
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
Write
H
H
L
READ (Select column and start READ burst)[74.75.83.]
WRITE (Select column and start new WRITE burst)[74.75.84.]
PRECHARGE[76.]
(With Auto
Precharge)
L
H
L
Note :
68. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh).
69. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m
(assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
70. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in
the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the
bank will be in the idle state.
71. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
72. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
73. All states and sequences not shown are illegal or reserved.
74. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
75. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst.
76. Burst in bank n continues as initiated.
77. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later.
78. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered.
DQM should be used twwo clock prior to the WRITE command to prevent bus contention.
79. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered,
with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
80. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered.
The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
81. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later.
The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 25.) .
82. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 26. ).
83. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m(Figure 27. ).
84. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered.
The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one
clock prior to the WRITE to bank m (Figure 28. ).
45
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
