CMS4A16LAx–75Ex
T0
T2
T3
T1
T4
T5
T6
T7
CLK
Read-AP
Bank n
Read-AP
Bank m
Command
NOP
NOP
NOP
NOP
NOP
NOP
Internal States
tRP - Bank m
tRP - Bank n
Page
Active
Read with a Burst of 4
Interrupt Burst, Precharge
Read with Burst of 4
Idle
Bank n
Bank m
Page Active
Precharge
Bank n
Col a
Bank m
Col d
Address
DQ
Dout
a
Dout
a+1
Dout
d
Dout
d+1
CAS Latency=3(Bank n)
CAS Latency=3(Bank m)
Figure 25. Read with Auto Precharge Interrupted by a Read(CAS Latency =3)
T0
T2
T3
T1
T4
T5
T6
T7
CLK
Read-AP
Bank n
Write-AP
Bank m
NOP
Command
NOP
NOP
NOP
NOP
NOP
Internal States
tRP - Bank n
tWR - Bank m
Page
Active
Read with a Burst of 4
Interrupt Burst, Precharge
Write with Burst of 4
Idle
Bank n
Bank m
Page Active
Write-Bank
Bank m
Col d
Bank n
Col a
Address
DQM
Dout
a
Din
d
Din
d+1
Din
d+2
Din
d+3
DQ
CAS Latency=3(Bank n)
Figure 26. Read With Auto Precharge Interrupted by a Write(Read CAS Latency =3)
40
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
