CMS4A16LAx–75Ex
Table 9. CKE[50.51.52.53.]
CKEn-1
.
CKEn
Current State
Commandn
Actionn
Power Down
Self Refresh
X
X
X
Maintain Power Down
Maintain Self Refresh
Maintain Clock Suspend
L
L
L
Clock Suspend
Power Down[54.]
Self Refresh[55.]
Command Inhibit or NOP
Command Inhibit or NOP
Exit Power Down
Exit Self Refresh
H
Clock Suspend[56.]
All Banks Idle
X
Exit Clock Suspend
Power Down Entry
Command Inhibit or NOP
H
L
All Banks Idle
Auto Refresh
Valid
Self Refresh Entry
Reading or Writing
Clock Suspend Entry
H
H
See Table 10.
Note :
50. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
51. Current State is the state of the SDRAM immediately prior to the clock edge n.
52. Commandn is the command registered at clock edge n , and Actionn is a result of Commandn.
53. All states and sequences not shown are illegal or reserved.
54. Exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the tCKS is met)
55. Exiting self refresh at clock edge n will put the device in all the banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges
occuring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period.
56. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
Table 10. Current State Bank n, Command to Bank n[57.58.59.60.61.62.]
.
Current State
CS#
RAS#
CAS#
WE#
Command(Action)
H
L
L
L
L
L
X
H
L
L
L
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH[63.]
Any
Idle
L
LOAD MODE REGISTER [63.]
H
L
PRECHARGE [67.]
Note :
57. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9. ) and after tXSR has been met (if the previous state was self refresh).
58. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
59. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
60. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank
should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10. and according to
Table 11. . Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating:
Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled:
Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle
state.
61. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these
states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing
Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle
state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state.
62. All states and sequences not shown are illegal or reserved.
63. Not bank-specific; requires that all banks are idle.
64. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
65. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
66. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
67. Does not affect the state of the bank and acts as a NOP to that bank.
43
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
