CMS4A16LAx–75Ex
CLK
CKE
>=tCKS
tCKS
NOP
NOP
Active
Command
tRCD
tRAS
tRC
All banks Idle
Input buffers gated off
Enter Power Down Mode
Exit Power Down Mode
Figure 22. Power Down
suspend mode is exited by registering CKE HIGH; the internal
clock and related operation will resume on the subsequent
positive clock edge.
CLOCK SUSPEND
The clock suspend mode occurs when a column access/
burst is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic. For each positive clock edge on which
CKE is sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the input pins
at the time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst-
counters are not incremented, as long as the clock is sus-
pended. (See examples in Figure 23. and Figure 24. .) Clock
BURST READ/SINGLE WRITE
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the progra-
mmed burst length. The burst read/single write mode is entered
by programming the write burst mode bit (M9) in the mode
register to a logic 1. READ commands access columns
according to the programmed burst length and sequence.
37
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
