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HCPL2630SV 参数 Datasheet PDF下载

HCPL2630SV图片预览
型号: HCPL2630SV
PDF下载: 下载PDF文件 查看货源
内容描述: 高速的10Mbit / s的逻辑门光电耦合器 [High Speed 10MBit/s Logic Gate Optocouplers]
分类和应用: 光电
文件页数/大小: 12 页 / 322 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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Electrical Characteristics (Continued)  
Transfer Characteristics (T = -40 to +85°C unless otherwise specified)  
A
Symbol  
DC Characteristics  
Test Conditions  
Min.  
Typ.* Max.  
Unit  
I
HIGH Level Output Current  
V
= 5.5V, V = 5.5V,  
100  
µA  
OH  
CC  
O
(2)  
I = 250µA, V = 2.0V  
F
E
V
LOW Level Output Current  
Input Threshold Current  
V
= 5.5V, I = 5mA, V = 2.0V,  
= 13mA  
.35  
3
0.6  
5
V
OL  
CC  
F
E
(2)  
I
CL  
I
V
= 5.5V, V = 0.6V, V = 2.0V,  
mA  
FT  
CC  
O
E
I
= 13mA  
OL  
Isolation Characteristics (T = -40°C to +85°C unless otherwise specified.)  
A
Symbol  
Characteristics  
Test Conditions  
Min.  
Typ.*  
Max.  
Unit  
I
Input-Output Insulation  
Leakage Current  
Relative humidity = 45%,  
1.0*  
µA  
I-O  
T = 25°C, t = 5s,  
A
(12)  
V
= 3000 VDC  
I-O  
V
Withstand Insulation Test  
Voltage  
RH < 50%, T = 25°C,  
2500  
V
RMS  
ISO  
A
(12)  
I
2µA, t = 1 min.  
I-O  
(12)  
12  
R
C
Resistance (Input to Output)  
V
= 500V  
10  
0.6  
I-O  
I-O  
(12)  
Capacitance (Input to Output) f = 1MHz  
pF  
I-O  
*All Typicals at V = 5V, T = 25°C  
CC  
A
Notes:  
1. The V supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic  
CC  
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible  
to the package V and GND pins of each device.  
CC  
2. Each channel.  
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.  
4. t  
– Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current  
PLH  
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.  
5. t – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current  
PHL  
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.  
6. t – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.  
r
7. t – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.  
f
8. t  
– Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input  
ELH  
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.  
9. t – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input  
EHL  
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.  
10. CM – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the  
H
HIGH state (i.e., V  
> 2.0V). Measured in volts per microsecond (V/µs).  
OUT  
11. CM – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the  
L
LOW output state (i.e., V  
< 0.8V). Measured in volts per microsecond (V/µs).  
OUT  
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted  
together.  
©2005 Fairchild Semiconductor Corporation  
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7  
www.fairchildsemi.com  
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