Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
0
AS
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
V
DD
V
GS
-
V
= 2V
DUT
GS
Q
gs2
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
0
DS
90%
90%
+
V
GS
V
DD
10%
10%
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
FDS3672 Rev. B
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
