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FDN338P 参数 Datasheet PDF下载

FDN338P图片预览
型号: FDN338P
PDF下载: 下载PDF文件 查看货源
内容描述: P沟道逻辑电平增强模式场效应晶体管 [P-Channel Logic Level Enhancement Mode Field Effect Transistor]
分类和应用: 晶体晶体管场效应晶体管
文件页数/大小: 4 页 / 88 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
I
D
= -250 µA, Referenced to 25
o
C
V
DS
= -16 V, V
GS
= 0 V
T
J
= 55°C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
(Note)
-20
-28
-1
-10
100
-100
V
mV/
o
C
µA
µA
nA
nA
BV
DSS
/
T
J
I
DSS
V
GS
= 8 V,V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
I
D
= -250 µA, Referenced to 25 C
V
GS
= -4.5 V, I
D
= -1.6 A
T
J
=125°C
V
GS
= -2.5 V, I
D
= -1.3 A
o
ON CHARACTERISTICS
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
-0.4
-0.6
2
0.115
0.16
0.155
-1
V
mV/
o
C
V
GS(th)
/
T
J
R
DS(ON)
0.13
0.22
0.18
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Note:
On-State Drain Current
Forward Transconductance
V
GS
= -4.5 V, V
DS
= -5 V
V
DS
= -5 V, I
D
= -1.6 A
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
-2.5
3
A
S
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note)
405
170
45
pF
pF
pF
SWITCHING CHARACTERISTICS
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
6.5
20
31
21
13
35
50
35
8.5
ns
ns
ns
ns
nC
nC
nC
V
DS
= -5 V, I
D
= -1.6 A,
V
GS
= -4.5 V
6
0.8
1.3
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42 A
(Note)
-0.42
-0.7
-1.2
A
V
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Typical R
θ
JA
using the board layouts shown below on FR-4 PCB in a still air environment :
a. 250
o
C/W when mounted on
0.02 in
2
pad of 2oz Cu.
a
b. 270
o
C/W when mounted on
a 0.001 in
2
pad of 2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDN338P Rev.D