E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
DEVICE BUS OPERATIONS
Several device operational modes are provided in
the ES29DL320 device. Commands are used to ini-
tiate the device operations. They are latched and
stored into internal registers with the address and
data information needed to execute the device
operation.
Simultaneous Read/Write Operation
This device is capable of reading data from one bank
of memory while programming or erasing in the
other bank of memory. An erase operation may also
be suspended to read from or program to another
location within the same bank (except the sector
being erased). Figure 33 shows how read and write
cycles may be initiated for simultaneous operation
with zero latency. Refer to the CMOS DC character-
istics Table11 for further current specification.
The available device operational modes are listed
in Table 1 with the required inputs, controls, and the
resulting outputs. Each operational mode is
described in further detail in the following subsec-
tions.
Word/Byte Mode Configuration ( BYTE# )
Read
The device data output can be configured by BYTE#
into one of two modes : word and byte modes. If the
BYTE# pin is set at logic ‘1’, the device is configured
in word mode, DQ0 - DQ15 are active and controlled
by CE# and OE#. If the BYTE# pin is set at logic ‘0’,
the device is configured in byte mode, and only data
I/O pins DQ0 - DQ7 are active and controlled by CE#
and OE#. The data I/O pins DQ8 - DQ14 are tri-
stated, and the DQ15 pin is used as an input for the
LSB (A-1) address.
The internal state of the device is set for the read
mode and the device is ready for reading array data
upon device power-up, or after a hardware reset. To
read the stored data from the cell array of the
device, CE# and OE# pins should be driven to V
IL
while WE# pin remains at V . CE# is the power
IH
control and selects the device. OE# is the output
control and gates array data to the output pins.
Word or byte mode of output data is determined by
the BYTE# pin. No additional command is needed
in this mode to obtain array data. Standard micro-
processor read cycles that assert valid addresses
on the device address inputs produce valid data on
the device data outputs. Each bank stays at the
read mode until another operation is activated by
writing commands into the internal command regis-
ter. Refer to the AC read cycle timing diagrams for
further details ( Fig. 18 ).
Standby Mode
When the device is not selected or activated in a
system, it needs to stay at the standby mode, in
which current consumption is greatly reduced with
outputs in the high impedance state.
6
Rev. 0E May 25, 2006
ES29DL320
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
