E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
The device enters the CMOS standby mode when
cycle and the last cycle with the program data and
addresses. In this mode, two unlock cycles are
saved ( or bypassed ).
CE# and RESET# pins are both held at Vcc
+0.3V.
(Note that this is a more restricted voltage range
than V ) If CE# and RESET# are held at V , but
IH.
IH
Sector Addresses
not within Vcc+0.3V, the device will be still in the
standby mode, but the standby current will be
greater than the CMOS standby current (15uA typi-
cally). When the device is in the standby mode, only
The entire memory space of cell array is divided
into a many of small sectors: 8kbytes x 8 boot sec-
tors and 64Kbytes x 63 main sectors. In erase
operation, a single sector, multiple sectors, or the
entire device (chip erase) can be selected for
erase. The address space that each sector occu-
pies is shown in detail in the Table 3-4.
standard access time (t ) is required for read
CE
access, before it is ready for read data. And even if
the device is deselected by CE# pin during erase or
programming operation, the device draws active cur-
rent until the operation is completely done. While the
device stays in the standby mode, the output is
placed in the high impedance state, independent of
the OE# input.
Accelerated Program Mode
The device offers accelerated program operations
through the ACC function. This is one of two func-
tions provided by the WP#/ACC pin. This function
is primarily intended to allow faster manufacturing
The device can enter the deep power-down mode
where current consumption is greatly reduced down
to less than 15uA typically by the following three
ways:
throughput at the factory. If the system asserts V
HH
(8.5~9.5V) on this pin, the device automatically
enters the previously mentioned Unlock Bypass
mode, temporarily unprotects any protected sec-
tors, and uses the higher voltage on the pin to
reduce the time required for program operations.
Only two-cycle program command sequences are
required because the unlock bypass mode is auto-
matically activated in this acceleration mode. The
- CMOS standby ( CE#, RESET# = Vcc + 0.3V )
- During the device reset ( RESET# = Vss + 0.3V )
- In Autosleep Mode ( after tACC + 30ns )
Refer to the CMOS DC characteristics Table11 for
further current specification.
device returns to the normal operation when V is
Autosleep Mode
HH
removed from the WP#/ACC pin. It should be
The device automatically enters a deep power-down
mode called the autosleep mode when addresses
noted that the WP#/ACC pin must not be at V for
HH
operations other than accelerated programming, or
device damage may result. In addition, the WP#/
ACC pin must not be left floating or unconnected;
inconsistent or undesired behavior of the device
may result.
remain stable for t
+30ns. In this mode, current
ACC
consumption is greatly reduced ( less than 15uA typ-
ical ), regardless of CE#, WE# and OE# control sig-
nals.
Autoselect Mode
Writing Commands
Flash memories are intended for use in applica-
tions where the local CPU alters memory contents.
In such applications, manufacturer and device
identification (ID) codes must be accessible while
the device resides in the target system ( the so
called “in-system program”). On the other hand,
signature codes have been typically accessed by
raising A9 pin to a high voltage in PROM program-
mers. However, multiplexing high voltage onto
address lines is not the generally desired system
design practice. Therefore, in the ES29DL320
device an autoselect command is provided to
allow the system to access the signature codes
without any high voltage. The conventional A9
high-voltage method used in the PROM program-
ers for signature codes are still supported in this
device.
To write a command or command sequences to ini-
tiate some operations such as program or erase, the
system must drive WE# and CE# to V , and OE# to
IL
V . For program operations, the BYTE# pin deter-
IH
mines whether the device accepts program data in
bytes or words. Refer to “BYTE# timings for Write
Operations” in the Fig. 21 for more information.
Unlock Bypass Mode
To reduce more the programming time, an unlock-
bypass mode is provided. Once a bank enters this
mode, only two write cycles are required to initiate
the programming operation instead of four cycles in
the normal program command sequences which are
composed of two unlock cycles, program set-up
7
Rev. 0E May 25, 2006
ES29DL320
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
