E S I
E S I
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During the unlock-bypass mode, only the unlock-
bypass program and unlock-bypass reset com-
mands are valid. To exit the unlock-bypass mode,
the system must issue the two-cycle unlock-bypass
reset command sequence. The first cycle must con-
tain the data 90h. The second cycle need to only
contain the data 00h. The device then returns to the
read mode.
Program Status Bits : DQ7, DQ6 or RY/BY#
When the Embedded Program algorithm is com-
plete, the device then returns to the read mode and
addresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write
Operation Status section Table 10 for information on
these status bits.
- Unlock Bypass Enter Command
- Unlock Bypass Reset Command
- Unlock Bypass Program Command
Any Commands Ignored during Program-
ming Operation
CHIP ERASE COMMAND
Any commands written to the device during the
Embedded Program algorithm are ignored. Note that
a hardware reset can immediately terminates the
program operation. The program command
sequence should be reinitiated once the device has
returned to the read mode, to ensure data integrity.
To erase the entire memory, a chip erase command
is used. This command is a six bus cycle operation.
The chip erase command sequence is initiated by
writing two unlock cycles, followed by a set-up com-
mand. Two additional unlock write cycles are then
followed by the chip erase command, which in turn
invokes the Embedded Erase algorithm. The chip
erase command erases the entire memory includ-
ing all other sectors except the protected sectors,
but the internal erase operation is performed on a
single sector base.
Programming from “0” back to “1”
Programming is allowed in any sequence and
across sector boundaries. But a bit cannot be pro-
grammed from “0” back to a ”1”. Attempting to do so
may cause the device to set DQ5 = 1, or cause the
DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations
can convert a “0” to a “1”
Embedded Erase Algorithm
The device does not require the system to prepro-
gram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the
entire memory for an all zero data pattern prior to
electrical erase. The system is not required to pro-
vide any controls or timings during these opera-
tions. Table 9 shows the address and data
requirements for the chip erase command
sequence. Note that the autoselect, and CFI modes
are unavailable while an erase operation is in
progress
Unlock Bypass
In the ES29LV160 device, an unlock bypass pro-
gram mode is provided for faster programming oper-
ation. In this mode, two cycles of program command
sequences can be saved. To enter this mode, an
unlock bypass enter command should be first written
to the system. The unlock bypass enter command
sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle contain-
ing the unlock bypass command, 20h. The device
then enters the unlock-bypass program mode. A
two-cycle unlock bypass program command
sequence is all that is required to program in this
mode. The first cycle in this sequence contains the
unlock bypass program set-up command, A0h; the
second cycle contains the program address and
data. Additional data is programmed in the same
manner. This mode dispenses with the initial two
unlock cycles required in the standard program com-
mand sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the
command sequence.
Erase Status Bits : DQ7, DQ6, DQ2, or RY/
BY#
When the Embedded Erase algorithm is complete,
the device returns to the read mode and addresses
are no longer latched. The system can determine
the status of the erase operation by using DQ7,
DQ6, DQ2, or RY/BY#. Refer to the Write Opera-
tion Status section Table 10 for information on these
status bits.
Commands Ignored during Erase Operation
Any command written during the chip erase opera-
tion are ignored. However, note that a hardware
21
Rev. 1C Jan 5 , 2006
ES29LV160D
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