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toggles when the system reads at addresses within
those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-
suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to
Table 6 to compare outputs for DQ2 and DQ6. Fig.
10 shows the toggle bit algorithm in flowchart form,
and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsec-
tion. Fig. 23 shows the toggle bit timing diagram.
Fig. 24 shows how differently DQ2 operates com-
pared with DQ6.
START
Read DQ7-DQ0
Read DQ7-DQ0
No
Toggle Bit
= Toggle ?
Yes
DQ5 = 1 ?
Yes
No
Read DQ7-DQ0
Twice
Reading Toggle Bits DQ6/DQ2
No
Toggle Bit
= Toggle ?
Refer to Fig. 10 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7-DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of
the toggle bit after the first read. After the second
read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or
erase operation. The system can read array data
on DQ7-DQ0 on the following read cycle. However,
if after the initial two read cycles, the system deter-
mines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no
longer toggling, the device has successfully com-
pleted the program or erase operation. If it is still
toggling, the device did not completed the operation
successfully, and the system must write the reset
command to return to reading array data. The
remaining scenario is that the system initially deter-
mines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read
cycles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, this sys-
tem must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Fig. 10).
Yes
Program/Erase
Operation
Complete
Program/Erase
Operation Not
Complete, Write
Reset Command
Note:
The system should recheck the toggle bit even if DQ5 = “1”
because the toggle bit may stop toggling as DQ5 changes to “1”.
See the subsections on DQ6 and DQ2 for more information.
Figure 10. Toggle Bit Algorithm
24
Rev. 1D January 5, 2006
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