XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
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Signaling data is embedded into the input PCM data coming from the Terminal Equipment
11.3.2 Insert Signaling Bits from TSCR Register
The four most significant bits of the Transmit Signaling Control Register (TSCR) of each timeslot can be used
to store outgoing signaling data. The user can program these bits through the microprocessor access. If the
XRT86L30 framer is configured to insert signaling bits from the TSCR registers, the DS1 Transmit Framer
block will strip off the least significant bits of each time slot in the signaling frames and replace it with the
signaling bit stored inside the TSCR registers. The insertion of signaling bits into PCM data is done on a per-
channel basis.
In SF or SLC®96 mode, the user can control the XRT86L30 framer to transmit no signaling (transparent), two-
code signaling, or four-code signaling. Two-code signaling is done by substituting the least significant bit (LSB)
of the specific channel in frame 6 and 12 with the content of the Signaling bit A of the specific TSCR register.
Four-code signaling is done by substituting the LSB of channel data in frame 6 with the Signaling bit A and the
LSB of channel data in frame 12 with the Signaling bit B of the specific channel's TSCR register. If sixteen-code
signaling is selected in SF format, only the Signaling bit A and Signaling bit B information are used.
In ESF mode, the user can control the XRT86L30 framer to transmit no signaling (transparent) by disable
signaling insertion, two-code signaling, four-code signaling or sixteen code signaling. Two-code signaling is
done by substituting the least significant bit (LSB) of the specific channel in frame 6, 12, 18 and 24 with the
content of the Signaling bit A of the specific TSCR register.
Four-code signaling is done by substituting the LSB of channel data in frame 6 and frame 18 with the Signaling
bit A and the LSB of channel data in frame 12 and frame 24 with the Signaling bit B of the specific channel's
TSCR register.
Sixteen-code signaling is implemented by substituting the LSB of channel data in frames 6, 12, 18, and 24 with
the content of Signaling bit A, B, C, and D of TSCR register respectively.
In N or T1DM modes, no robbed-bit signaling is allowed and the transmit data stream remains intact.
The table below shows the four most significant bits of the Transmit Signaling Control Register.
TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (ADDRESS = 0X0340H - 0X0357H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
7
Signaling Bit A
Signaling Bit B
Signaling Bit C
Signaling Bit D
R/W
R/W
R/W
R/W
This bit is used to store Signaling Bit A that is sent as the least significant
bit of timeslot of frame number 6.
6
5
4
This bit is used to store Signaling Bit B that is sent as the least significant
bit of timeslot of frame number 12.
This bit is used to store Signaling Bit C that is sent as the least significant
bit of timeslot of frame number 18.
This bit is used to store Signaling Bit D that is sent as the least significant
bit of timeslot of frame number 24.
11.3.3
Insert Signaling Bits from TxSig_n Pin
The XRT86L30 framer can be configured to insert signaling bits provided by external equipment through the
TxSig_n pins. This pin is a multiplexed I/O pin with two functions:
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•
TxCHN[0]_n - Transmit Timeslot Number Bit [0] Output pin
TxSig_n - Transmit Signaling Input pin
When the Transmit Fractional DS1 bit of the Transmit Interface Control Register (TICR) is set to 0, this pin is
configured as TxTSb[0]_n pin, it outputs bit 0 of the timeslot number of the DS1 PCM data that is transmitting.
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EXAR [ EXAR CORPORATION ]
