XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
4.7
T1/E1 Fractional Interface
The individual time slots can be enabled/disabled to carry fractional DS-0 data. The purpose of this interface is
to enable one or more time slots in the PCM data (TxSER) to be replaced with the fractional DS-0 payload. If
this mode is selected, the dedicated hardware pin TxCHN1/T1FR is used to input the fractional DS-0 data
within the time slots that are enabled. The dedicated hardware pin RxCHN1/R1FR is used to output the
fractional DS-0 data within the time slots that are enabled. Figure 14 is a simplified diagram of the Fractional
Interface.
F
IGURE 14. T1 FRACTIONAL INTERFACE
T1 Fractional Data
TSN - TSM
TxSER
F
PCM TS[0-(N-1)]
PCM TS[(M+1)-23]
TxCHN1/T1FR
TxSERclk
TxSYNC
TxMSYNC
149
EXAR [ EXAR CORPORATION ]
