XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
Table 119:: Framer Interrupt Enable Register T1 Mode ................................................................................................ 103
Table 120:: Data Link Status Register 1 ........................................................................................................................ 104
Table 121:: Data Link Interrupt Enable Register 1 ......................................................................................................... 105
Table 122:: Slip Buffer Interrupt Status Register (SBISR) ............................................................................................. 106
Table 123:: Slip Buffer Interrupt Enable Register (SBIER) ............................................................................................ 107
Table 124:: Receive Loopback Code Interrupt and Status Register (RLCISR) ............................................................. 107
Table 125:: Receive Loopback Code Interrupt Enable Register (RLCIER) ................................................................... 108
Table 126:: Receive SA Interrupt Register (RSAIR) ...................................................................................................... 108
Table 127:: Receive SA Interrupt Enable Register (RSAIER) ....................................................................................... 109
Table 128:: Excessive Zero Status Register .................................................................................................................. 109
Table 129:: Excessive Zero Enable Register ................................................................................................................. 110
Table 130:: SS7 Status Register for LAPD1 .................................................................................................................. 110
Table 131:: SS7 Enable Register for LAPD1 ................................................................................................................. 110
Table 132:: Data Link Status Register 2 ........................................................................................................................ 110
Table 133:: Data Link Interrupt Enable Register 2 ......................................................................................................... 112
Table 134:: SS7 Status Register for LAPD2 .................................................................................................................. 113
Table 135:: SS7 Enable Register for LAPD2 ................................................................................................................. 113
Table 136:: Data Link Status Register 3 ........................................................................................................................ 113
Table 137:: Data Link Interrupt Enable Register 3 ......................................................................................................... 115
Table 138:: SS7 Status Register for LAPD3 .................................................................................................................. 116
Table 139:: SS7 Enable Register for LAPD3 ................................................................................................................. 116
Table 140:: Customer Installation Alarm Status Register .............................................................................................. 116
Table 141:: Customer Installation Alarm Status Register .............................................................................................. 117
Table 142:: Microprocessor Register #556 Bit Description ............................................................................................ 118
Table 143:: Equalizer Control and Transmit Line Build Out ........................................................................................... 118
Table 144:: Microprocessor Register #557 Bit Description ............................................................................................ 121
Table 145:: Microprocessor Register #558 Bit Description ............................................................................................ 124
Table 146:: Microprocessor Register #559 Bit Description ............................................................................................ 126
Table 147:: Microprocessor Register #560 Bit Description ............................................................................................ 127
Table 148:: Microprocessor Register #561 Bit Description ............................................................................................ 128
Table 149:: Microprocessor Register #562 Bit Description ............................................................................................ 130
Table 150:: Microprocessor Register #563 Bit Description ............................................................................................ 130
Table 151:: Microprocessor Register #564 Bit Description ............................................................................................ 131
Table 152:: Microprocessor Register #565 Bit Description ............................................................................................ 131
Table 153:: Microprocessor Register #566 Bit Description ............................................................................................ 132
Table 154:: Microprocessor Register #567 Bit Description ............................................................................................ 132
Table 155:: Microprocessor Register #568 Bit Description ............................................................................................ 133
Table 156:: Microprocessor Register #569 Bit Description ............................................................................................ 133
Table 157:: Microprocessor Register #570 Bit Description ............................................................................................ 134
Table 158:: Microprocessor Register #571 Bit Description ............................................................................................ 134
Table 159:: Microprocessor Register #700 Bit Description - Global Register 0 ............................................................. 135
Table 160:: Microprocessor Register #701, Bit Description - Global Register 1 ............................................................ 135
Table 161:: Microprocessor Register #702, Bit Description - Global Register 2 ............................................................ 136
Table 162:: Microprocessor Register #703, Bit Description - Global Register 3 ............................................................ 136
Table 163:: Microprocessor Register #704, Bit Description - Global Register 4 ............................................................ 137
Table 164:: List of the Possible Conditions that can Generate Interrupts, in each Framer ........................................... 138
Table 165:: Address of the Block Interrupt Status Registers ......................................................................................... 139
Table 166:: Block Interrupt Status Register ................................................................................................................... 139
Table 167:: Block Interrupt Enable Register .................................................................................................................. 141
Table 168:: Interrupt Control Register ........................................................................................................................... 142
Table 169:: Framing Format for PMON Status Inserted within LAPD by Initiating APR ................................................ 168
Table 170:: Random Bit Sequence Polynomials ........................................................................................................... 185
Table 171:: Short Haul Line Build Out ........................................................................................................................... 186
Table 172:: Selecting the Internal Impedance ............................................................................................................... 189
Table 173:: Selecting the Value of the External Fixed Resistor ..................................................................................... 189
Table 174:: The mapping of T1 frame into E1 framing format ....................................................................................... 211
Table 175:: Bit Format of Timeslot 0 octet within a FAS E1 Frame ............................................................................... 249
Table 176:: Bit Format of Timeslot 0 octet within a Non-FAS E1 Frame ....................................................................... 250
Table 177:: Bit Format of all Timeslot 0 octets within a CRC Multi-frame ..................................................................... 251
Table 178:: Superframe Format ..................................................................................................................................... 257
X
EXAR [ EXAR CORPORATION ]
