XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.1.1
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
T
D0:D7
S
T
S
D0:D7
D0:D7
T
S D0:D7
T
D0:D7
T
D0:D7
T
TSRT
IER[1]
enabled
ISR is read
TX FIFO no
longer empty
INT*
TSI
TWRI
TX FIFO
Empty
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
T
D0:D7
S
T
S
D0:D7
D0:D7
T
S D0:D7
T
D0:D7
T
D0:D7
T
IER[1]
enabled
ISR is read
TSRT
TX FIFO no
longer empty
TSI
INT*
TWRI
TX FIFO
Empty
At least 1
empty location
in FIFO
TX FIFO
Full
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA
42
EXAR [ EXAR CORPORATION ]
